2015.2:
 * Version 2.0 (Rev. 7)
 * No changes

2015.1:
 * Version 2.0 (Rev. 7)
 * Updated IP to get Bus Width from common utilities for Board.
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 2.0 (Rev. 6)
 * No changes

2014.4:
 * Version 2.0 (Rev. 6)
 * No changes

2014.3:
 * Version 2.0 (Rev. 6)
 * Example design updated to have ATG mask change dynamically based on GPIO widths
 * AXI GPIO uses new libraries and axi_lite_ipif subcores
 * Updating core to use utils.tcl needed for board flow from common location
 * Disabling customization of the appropriate GPIO if board interface has been used

2014.2:
 * Version 2.0 (Rev. 5)
 * Example design XDC update for timing DRC
 * Updated board flow commands in sync with internal flow updates, no functional changes.

2014.1:
 * Version 2.0 (Rev. 4)
 * Internal device family name change, no functional changes
 * Virtex UltraScale Pre-Production support.

2013.4:
 * Version 2.0 (Rev. 3)
 * Board interface connection for GPIO2 enabled by default
 * Updated Example design to use Clocking Wizard to generate clocks
 * Kintex UltraScale Pre-Production support

2013.3:
 * Version 2.0 (Rev. 2)
 * Added example design and demonstration testbench
 * Reduced warnings in synthesis and simulation
 * Enhanced support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
 * Improved GUI speed and responsiveness, no functional changes

2013.2:
 * Version 2.0 (Rev. 1)
 * Enable support for future devices
 * There have been no functional or interface changes to this IP.

2013.1:
 * Version 2.0
 * Native Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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