2015.2:
 * Version 5.0 (Rev. 7)
 * No changes

2015.1:
 * Version 5.0 (Rev. 7)
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 5.0 (Rev. 6)
 * No changes

2014.4:
 * Version 5.0 (Rev. 6)
 * No changes

2014.3:
 * Version 5.0 (Rev. 6)
 * Modified to use new sub-cores in place of proc_common,no functional changes
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
 * Updated core to use utils.tcl, needed for board flow from common location

2014.2:
 * Version 5.0 (Rev. 5)
 * Enhanced support for IP Integrator
 * Board flow related updates, no functional changes

2014.1:
 * Version 5.0 (Rev. 4)
 * Internal device family name change, no functional changes

2013.4:
 * Version 5.0 (Rev. 3)
 * Added exdes.xdc file
 * Changed the associated resets for slowest_sync_clk
 * Kintex UltraScale Pre-Production support

2013.3:
 * Version 5.0 (Rev. 2)
 * Changed board flow specific parameter name as per new requirements
 * Added example design and demonstration testbench
 * Reduced warnings in synthesis and simulation
 * Enhanced support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
 * Support for 7-series devices at Production status

2013.2:
 * Version 5.0 (Rev. 1)
 * Added BETA support for future devices.
 * No other RTL updates

2013.1:
 * Version 5.0
 * Updated version for 2013.1
 * Updated bd.tcl for board flow
 * No other RTL updates

(c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.

DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.

CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
