2015.2:
 * Version 5.5 (Rev. 1)
 * No changes

2015.1:
 * Version 5.5 (Rev. 1)
 * Added support and functionality  for Secure and Non-Secure
 * Removed wire ENET0_GMII_TX_EN_i
 * Wire  ENET0_GMII_TX_ER_i; and the signals were tied low
 * Added functionality for TRACE_CTL_PIPE
 * Secure/Non-Secure Access configuration Enablement added in General settings
 * DDR training board details were updated with revised scale and correct values
 * Writing to register tpiu  Curentsize (0xF8803004) register is removed if trace is disabled
 * Dynamic Trace Pipeline width configuration based on user choice
 * Adding keep option for Trace Control & Data registers
 * If JTAG OBUF is disabled; the PJTAG_TDO is set to ‘0’

2014.4.1:
 * Version 5.5
 * No changes

2014.4:
 * Version 5.5
 * No changes

2014.3:
 * Version 5.5
 * The custom time stamp unit(PTP) signals will be exposed to the Programmable Logic(PL), even when the Ethernet is routed through the MIO. For more details, please refer Zynq Technical Reference Manual (UG 585) CH No. 16.4 IEEE 1588 Time Stamping. This change enables additional optional functionality for designs with Ethernet on MIO. No changes are required for existing designs
 * Updated Trace data port width dependency to be based on Trace parameters Port width will display based on user selection
 * Updated the JTAG interface from master to slave mode. Based on Zynq Technical Reference Manual, PS boot mode supports 4 master boot mode and 2 Slave JTAG Boot mode. Prior versions of Zynq PS7 IP had PL JTAG in master mode incorrectly. The JTAG port TDO will have a buffer (OBUFT) instantiated as part of the Processing System7 IP. This change only affects designs which use PL JTAG through EMIO interface. For More details, refer chapter no.6 of Zynq Technical Reference Manual (UG 585) - Boot and Configuration
 * Added range validation for SMC cycle parameters
 * Prior versions of PS7 IP had writes to certain reserved bits of DDR IOB Buffer Control (DDRIOB_DDR_CTRL). These have been fixed to 0x0.

2014.2:
 * Version 5.4 (Rev. 1)
 * Add the polarity feature for reset (USB, I2C and Ethernet) pins
 * Add the IP type is processor
 * Fixed LPDDR2 hang Issue

2014.1:
 * Version 5.4
 * IRQ_F2P connections to be made directly in the silicon

2013.4:
 * Version 5.3 (Rev. 1)
 * DDRIOB_SLEW registers added in ps7_init
 * Removed toggling of FPGA_RST_CTRL register from post_config
 * Trace enabled for different port size such as  2,4,8,16 and 32 bits

2013.3:
 * Version 5.3
 * Added Microzed board preset In ps7 ip
 * xz0303 SBG package added
 * TCL based preset support  for Zynq
 * Zynq BFM subcore added for simulation support

2013.2:
 * Version 5.2
 * Zynq Power Estimation Support added
 * Extended addresing support for SMC memories, QSPI memory, PS registers and SLCR registers
 * Peripheral I/O pin page made more user interactive

2013.1:
 * Version 5.01
 * Added support for ps7 preset configurations
 * Multiple silicon version support
 * Ps7 gui enhanced to vivado standard

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