# Compile Menu

## Compile one line

> The cell compiler is a specific tool designed for the automatic creation of CMOS cells from logic description. Click on Compile -> Compile One Line. The menu below appears. The default equation corresponds to a 3 input NOR gate. If needed, one can use the keyboard in order to modify the equation and then click on Compile. The gate is compiled and its corresponding layout is generated.

> The first item of the one-line syntax corresponds to the output name.

> The letter is followed by the sign " = ", the optional sign not " ~ ", and by the list of input names separated by the operators AND " & " or OR " | ". If need be, parenthesis can be added.

> The input and output names are 8 character strings maximum.

> Cell | Formula
> Inverter | out=~in
> NAND gate | n=~(a&b)
> 3 Input OR | s=a|b|c
> 3 Input NAND | out=~(a&b&c)
> AND-OR Gate | cgate=a&(b|c)
> CARRY Cell | cout=(a&b)|(cin&(a|b))

> TRANSISTOR SIZE. The default device size is given by the design rules. You may change the nMOS and pMOS width in the option menu before clicking on PILE.

> IMPLEMENTATION. The p-channel transistors are located on the top of the n-channel transistor net. If some layout already exists near those icons, the cell origin is moved to the right until enough free space is found. If the '~' NOT operator has not been specified after the '=' sign, an inverter is added at the right hand side of the compiled cell. That is why an AND gate is compiled as a NAND gate followed by an inverter.

## Compile Verilog File

> The cell compiler can handle layout generation from a primitive-based VERILOG description text into a layout form automatically. Click on Compile -> Compile Verilog File. Select a VERILOG text file and click on "Generate". The list of primitives is given below.

> PRIMITIVE | NODES | EXAMPLE
> dreg | Inputs : Data,RESET, CLOCK; Outputs: Q, nQ | dreg reg1(d,rst,h,q,nq);
> Inv, not | Inputs : IN; Outputs: OUT | inv inv1(s,e); // both ‘inv’ and ‘not’ can be used
> and | Inputs : 2 to 4; Outputs: S | and and1(s,a,b,c,d); // limit inputs to 4
> nand | Inputs : 2 to 4; Outputs: S | nand nand1(s,a,b,c,d);
> or | Inputs : 2 to 4; Outputs: S | or or3(s,a,b,c);
> nor | Inputs : 2 to 4; Outputs: S | nor my_nor4(s,a,b,c,d);
> xor | Inputs : a,b; Outputs: S | xor xor_gate(xor_out,d0,d1);
> Nmos | Inputs: gate, source; Outputs: drain | nmos nmos1(d,s,g);
> Complex Gate | <Assign><output>=<combination of inputs> (& = AND, |=OR, ~=NOT) | assign out2=(B3&A3)|(w20&(B3|A3))

> An example of compilation from VERILOG to layout is illustrated below.

> ##

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