2015.4:
 * Version 2.1 (Rev. 7)
 * Revision change in one or more subcores

2015.3:
 * Version 2.1 (Rev. 6)
 * Updated to use blk_mem_gen v8.3 and fifo_generator v13.0
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Revision change in one or more subcores

2015.2.1:
 * Version 2.1 (Rev. 5)
 * No changes

2015.2:
 * Version 2.1 (Rev. 5)
 * No changes

2015.1:
 * Version 2.1 (Rev. 5)
 * Improved automation of NUM_READ_OUTSTANDING and NUM_WRITE_OUTSTANDING IP Integrator Interface properties when FIFO_MODE > 0
 * The support status for Kintex UltraScale is changed from Pre-Production to Production.

2014.4.1:
 * Version 2.1 (Rev. 4)
 * No changes

2014.4:
 * Version 2.1 (Rev. 4)
 * Internal device family change, no functional changes

2014.3:
 * Version 2.1 (Rev. 3)
 * Eliminated unnecessary stalling of m_axi_arvalid output due to ID changes under some conditions. IP now supports propagating multiple outstanding transactions regardless of ID value, as stated in the Prodcut Guide.
 * Removed extraneous combinatorial pathway from m_axi_bvalid to m_axi_bready in downsizer configuration.
 * Warning reduction in downsizer configuration.
 * Updated configuration GUI to show transaction splitting information when downsizing

2014.2:
 * Version 2.1 (Rev. 2)
 * No changes

2014.1:
 * Version 2.1 (Rev. 2)
 * Internal device family name change, no functional changes
 * Updated IP-level XDC to reduce DRC warnings
 * Updated internal FIFOs to fifo_generator_v12_0 and blk_mem_gen_v8_2.

2013.4:
 * Version 2.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Broadened core-level XDC timing constraints to cover all async CDCs (if any), regardless of target family implementation.

2013.3:
 * Version 2.1
 * Added parameter SYNCHRONIZATION_STAGES to specify clock synchronizer stages (passed to internal fifo_generator when performing async clock conversion).
 * Fixed RDATA and RRESP value corruption for rare corner cases when upsizing using the FIFO_MODE feature.
 * Update IP-level XDC with false-path in async clock conversion path.
 * Eliminate extraneous pipeline registers in aresetn input paths.
 * Enhanced upsizer single-threading behavior to allow transactions with any ID to propagate without stalling (any FIFO mode setting), reducing overall latency of multi-threaded traffic ~0.15x.
 * Added example design.
 * Reduced warnings in synthesis and simulation.
 * Added support for Cadence IES and Synopsys VCS simulators.
 * Internal FIFO buffers updated to use FIFO Generator v11.0.

2013.2:
 * Version 2.0 (Rev. 1)
 * Repackaged to enable internal version management, no functional changes.
 * Constraints processing order changed.

2013.1:
 * Version 2.0
 * Native Vivado Release
 * Supports IP Integrator
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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