Course Description
Within the vast and ever-changing world of electronic system-on-chip (SoC) design, we explore system- and RT-level design methodology and tools, reviewing challenges and opportunities, current state-of-the-art and future trends. More specifically, the Embedded Systems course is organized into two modules: a) System-level Design Methodology, Languages and Tools and b) RTL Languages and Design Tools. In both modules, students are exposed to cutting-edge technology for embedded SoC design through the study of important recent research publications, the use of available commercial or open source design tools and the development and evaluation of rough subsystem prototypes or protocols.
-System-on-Chip
-Embedded Systems Architecture
-Semiconductor Industry Market
-Foundation IP and Star IP
-Multicore SoC: ST Nomadik Basic Principle
-Automotive Industry
-Trends in Automotive Industry
-Electronic System Level Design for SoC
-Separation of Concerns: Behavior & Communication
-Refinement Methodology & Partitioning
-Models of Computation
-Modeling to FPGA Prototyping
-Design Languages: Overview
-History of SystemC
-Original OSCI Structure
-SystemC Model Development
-Introduction to Data Types
-ArbitraryWidth Bit Type: sc_bv
-Module Ports
-Module Instantiation & Port Connection
-Example of sc_method
-Accessing Ports and Signals
-Example of Signal Binding
-Time Functions
-Example of wait
-ML505 Standard IP Design Overview
-Standard IP Added or Modified
-Software Requirements
-Using the Pre-Built Design
-Add Standard IP to BSB Design
-Extracting the Base Design
-Add Standard IP
-Connect Buses
-IP Configuration
-Connect IP Ports
-Generate Addresses
-Software Configuration
-Software Platform Settings
-Create MFS Image
-Compile Standard IP Design
-Generate the ELF Files
-Generate the Bitstream
-Loading a Bootloop ELF into the Block RAM
-Running the Lwipdemo Application
-Create an ACE File
-References
-Design Methodology
-Y Chart
-System Synthesis
-Bottom-Up Design
-Meet in the Middle Design II
-System Design
-FPGA Design
-Programming Models
-Determinism
-Synchronous Dataflow (SDF)
-State-Based Models
-Process State Machines
-Abstraction Levels
-Transport Layer
-Protocol, Physical Layers
-Specification Model
-Cycle-Accurate Model (CAM)
-Summary and Conclusions
-SystemC – Ongoing & Future Work
-Overview of Statistics Classes
-Parallel & Distributed Simulation
-Block & Stream Ciphers
-Hardware Ciphers
-Mapping onto NoC Topology - Graphics
-Application Model
-Mapping Task Graphs using SCOTCH
-Finite Element Methods: Unstructured
-Mapping onto NoC Topology - Results
-Mapping onto NoC Topology - Graphics
-References - NoC &Application Mapping
-Theoretical Metrics
-Web Resources
-Introduction – Embedded Systems
-Typical MPSoC : a platform with CPUs, GPUs, DSP, …
-Systems on Chip
-Computational
-Interact (sense, manipulate, communicate) with the external world: sensors, actuators
-Reactive: at the speed of the environment
-Heterogeneity: hardware/software blocks, mixed architectures
-Networked: shared, adaptive, sensor networks (buildings, environmental monitoring), smart products, wearable computing
-Flexibility: can run/implement multiple applications sequentially or concurrently - concurrency
-Reprogrammability/reconfigurability: flexibility in upgrading, bug fixing, product differentiation, product customization
-Part of a larger system (system within system)
-Performance and constraints:
–Timing (frequency, latency, throughput)
–Cost, power, area, weight, temperature, reliability
-Algorithmic level
-Register Transfer Level
-Level of description most suitable for synthesis
-Logic (gate) level
-Circuit (transistor) level
-Physical (layout) level
-VHDL Fundamentals
-Naming and Labeling
-Entity declaration – simplified syntax
-Fundamental parts of a library
-FPGAs
-FPGA Tool Flow
-System on Chip (SoC)
-SoC Tool Flow
-Demonstration
-HDL Synthesis
-Place and Route
-Traditional Embedded System
-Configurable System-on-Chip
-Bus Architecture: CoreConnect
-MicroBlaze Configuration
-Design Flow (Software)
Agenda
Announcements
ALL ANNOUNCEMENTS...-
Sunday, May 31, 2026, 8:56 AM
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Wednesday, May 13, 2026, 12:01 PM
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Thursday, May 7, 2026, 10:08 AM
Open Academic Course
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